Static timing analysis plays an important role in defining circuit performance for today's high-speed integrated circuits. Static timing analysis tools identify all the structural paths in the design and the calculated delay along each one of these paths. As commonly used, the term ‘path’ refers to two nodes in a circuit design coupled by one or more circuit devices. Typically, these paths start at a latch point and end at another latch point in the design. These paths are sorted according to their delay and the slowest (critical) paths in the design are identified. The designer then would have to work on these paths and try to optimize them to reduce the delay along these long paths in order to meet target performance frequency goals. Unfortunately, not all the paths identified by the static timing analysis tools are “true paths” because these paths cannot be activated in the design with various constraints. In other words, structural paths in a design that cannot be logically manipulated by signals or activated are called “false paths”. This leads to a pessimistic estimation of the speed of the design and can also lead to wasted effort in trying to optimize or reduce the delay along these so called false paths. In industry today the problem of dealing with false paths is handled manually by the designers. Typically, false path analysis and any following corrective action just result in wasted engineering effort and underestimation of the performance of the design. Researchers have addressed this problem of identifying false paths and there are two broad classes of techniques based on how to evaluate the constraints associated with the various paths. One of these major techniques uses symbolic methods based on Binary Decision Diagrams (BDDs). These techniques suffer from memory and run time complexities. The other class of techniques models the problem as an instance of Boolean satisfiability (SAT) and use SAT solvers. Again, these techniques cannot handle the size and complexities of today's industrial circuits. Others have proposed modeling techniques to improve the timing analyzers themselves so that the timing analyzers avoid identifying false paths to start with. However, none of these techniques are commercially practical, as they require making extensive modifications to the design model and only work for circuits that are made out of simple gates and under the unit gate delay assumptions. A unit gate delay assumption is the assumption that each gate has associated with it an equal unit of delay. These techniques are generally not practical in commercial circuits. Previous research has indicated that for most circuits only a small percentage of the paths in the circuit are actually true paths or synthesizable paths. There are two reasons why paths are found to be false paths. One reason has to do with combinational constraints associated with the paths within the combinational logic surrounding the path. The second reason is a result of sequential constraints associated with the state values required to activate the paths. Sequential constraints may prevent certain paths from ever assuming state values that would enable such paths to be true paths. Known techniques used to analyze complex circuit designs for the detection of and correction of false paths are expensive, slow and sometimes inaccurate.